1. The Field of the Invention
The present invention relates to semiconductor devices and methods for the fabrication of semiconductor devices. More specifically, the present invention provides a method for constructing vias in semiconductor devices.
2. The Relevant Art
Manufacturers of semiconductor devices have turned in recent years to the construction of multiple, substantially parallel layers of circuits on a single chip in order to increase the transistor density of the chip and, thereby, the computational efficiency of the semiconductor device. Typically, the substantially parallel layers are connected through "vias"--channels extending through the dielectric layers that electrically isolate the different layers of circuitry. In general, a via is fabricated by preparing an aperture through the dielectric layer separating two electrically conductive layers. These electrically conductive layers typically are a metal such as aluminum, or copper, or they can be made from gold.
FIGS. 1A and 1B show a typical semiconductor device at 100. Generally a semiconductor device includes a substrate 102, made from a material such as silicon (Si) or gallium arsenide (GaAs), upon which is deposited a layer of a conductive material 104, such as a metal. Upon metal layer 104 is typically provided an etch stop or anti-reflective coating (ARC) 106. Over the etch stop is deposited a dielectric layer 108, usually a non-conducting oxide such as silicon dioxide (SiO.sub.2). Over the oxide layer is provided a layer of photoresist 110 which is used during the lithography process to map the next layer of circuitry.
Traditionally, vias, such as via 112 in FIGS. 1A and 1B, are created by etching the photoresist and oxide down to the etch stop so that direct contact with the underlying metal is avoided. This is done primarily to avoid two undesirable processing difficulties. First, stopping the etch process at the etch stop layer avoids the well-known punch through effect. Second, etching through the etch stop layer to the underlying metal layer causes the formation of polymeric debris 114 that is extremely difficult to remove from the via. The polymeric debris is formed as a result of the plasma bombardment of the semiconductor device during the formation of the via and typically includes as its components the chemical species being used to create the plasma in addition to atoms from the metal layer, as well as atoms from the oxide, etch stop, and photoresist layers. For example, where carbon tetrafluoride (CF.sub.4) is used as the processing gas, SiO.sub.2 is used as the oxide layer, aluminum (Al) is used as the metal layer, and titanium tungsten (TiW) is used as the ARC, the polymeric debris formed in the via comprises polytetrafluoroethylene ((C.sub.2 F.sub.2).sub.n) in addition to atoms of oxygen, silicon, titanium, and aluminum. Under current processing techniques, the removal of such polymeric debris to form the finished via surfaces 116, 118 typically requires a wet etchant and several processing steps that can degrade chemically the metal layer. Without removal, the polymeric debris impairs the reliability and yield of the final semiconductor product.
In general, titanium nitride (TiN) is a preferred material to use as an etch stop, as it has the advantage of generating fewer particle-related problems during deposition. Unfortunately, TiN is also characterized by poor selectivity during the oxide etching used in the formation of vias. After partial removal of the underlayer during the above-described etching process currently used, the TiN layer within each via 116 has a different thickness throughout the wafer according to the wafer topography. This heterogeneous surface structure creates contact resistance and increases electrical resistivity within the via. Thus, although TiN has very good properties in some aspects, the drawbacks with respect to etching the TiN etch stop layer are so severe that this material is typically replaced with titanium tungsten (TiW).